A First Look at RISC-V Virtualization from an Embedded Systems Perspective

This article describes the first public implementation and evaluation of latest version RISC-V hypervisor extension (H-extension v0.6.1) specification in a Rocket chip core. To perform meaningful for modern multi-core embedded mixedcriticality systems, we have ported Bao, an open-source static partitioning hypervisor, to RISC-V. We also extended platformlevel interrupt controller (PLIC) enable direct guest injection with low deterministic latency enhanced timer infrastructure avoid trap emulation overheads. Experiments were carried out FireSim, cycle-accurate, FPGA-accelerated simulator, system was successfully deployed tested Zynq UltraScale+ MPSoC ZCU104. Our hardware opensourced is currently use by community towards ratification H-extension specification.